The invention relates to electronic devices, and, more particularly, to error correction coding.
Digital communication and storage systems typically include error correction coding in order to overcome errors arising from the transmission or storage medium. Forward error-correction coding (FEC) systems add redundancy to the transmitted signal so that the receiver can detect and correct errors using only the received signal. This eliminates the need for the receiver to send requests for retransmission to the transmitter.
One of the more popular error correction code types is Reed-Solomon code. Reed-Solomon codes are block codes with maximum distance separation and are highly efficient in their use of redundancy. The most appealing aspect of Reed-Solomon codes is the availability of efficient decoding algorithms. See for example, Wicker and Bhargava (Eds.) Reed-Solomon Codes and Their Applications (IEEE Press, Piscataway, N.J., 1994).
FIG. 1 shows a high level view of a Reed-Solomon coding system. A block of information bits, I, is encoded into a codeword C which is a larger block that contains the original information and redundant bits. After transmission over a channel, the received block of bits can be represented as C+E where E is a block of error bits. The decoder generates Ixe2x80x2 from C+E, and Ixe2x80x2 will equal I if the number of errors bits in E is within the correction capabilities of the code.
FIG. 2 shows a more detailed description of Reed-Solomon coding. In particular, a block of bk information bits is divided into k groups of b bits and each group of b bits is represented by a symbol, producing a block of k information symbols for coding. The encoder operates on the block of k information symbols to produce a block of n codeword symbols containing the original information in some form as well as redundancy. The code can be designed so that the redundancy is used for error detection only, error correction only, or a combination of some error detection and some error correction. The block of n coded symbols is then translated into a block of bn bits and transmitted over the channel. The receiver front-end produces a block of bn bits that might be corrupted, depending upon the amount of channel distortion. The block of bn bits is translated into a block of n symbols and processed with the decoder. As long as the transmission errors lead to at most (nxe2x88x92k)/2 erroneous symbols, a hard-decision decoder can reliably recover the input k information symbols and input bk bits. The price paid for the added redundancy is the increase in the number of symbols to transmit by a factor of n/k. Of course, this means an information decrease by a factor of k/n for a constant transmission rate.
Reed-Solomon encoding essentially maps k information symbols with the symbols as elements of a finite field (Galois field or GF) with a power of 2 number of elements into n symbols which are GF elements from the same finite field to form a codeword. Note that for such field with 2M elements, denoted GF(2M), the elements can be represented by M-bit words and the nonzero elements can be expressed as powers of a primitive element xcex1. That is, the elements of GF(2M) are 0, 1, xcex1, xcex12, . . . , xcex1q where q=2Mxe2x88x922.
Nonsystematic Reed-Solomon encoding produces codewords by distributing the information and redundancy across the entire codeword of n symbols according to the coding algorithm. Systematic Reed-Solomon encoding, on the other hand, forms codewords by concatenating the k information symbols with nxe2x88x92k parity symbols, which are computed according to the coding algorithms. The additional nxe2x88x92k parity symbols contain the redundant information that is used by the receiver to choose the most likely transmitted k information symbols. In particular, with receiver soft decision the nxe2x88x92k parity symbols can be used to correct e error symbols and detect s erased symbols provided 2e+s is at most nxe2x88x92k. Note that values such as n=204 and k=188 with the GF being GF(28) (the finite field with 256 elements) are not uncommon. Indeed, this is a commonly used code for high speed modems and would be called a (204,188) code. This code can correct 8 error symbols per 204-symbol codeword.
Systematic Reed-Solomon encoding is advantageous because the information component of the received codeword can be extracted at the receiver without applying the Reed-Solomon decoding operations. The first k symbols represent all of the information. The last nxe2x88x92k symbols must be computed from the information symbols.
The parity symbols can be computed from the information symbols using methods based on the arithmetic of polynomials whose coefficients are GF elements with the elements representing groups of bits. The information, parity, and codewords are represented by polynomials I(x), P(x), and C(x), respectively. For systematic Reed-Solomon encoding C(x)=xnxe2x88x92kI(x)+P(x) with P(x) the remainder from the polynomial division of xnxe2x88x92kI(x) by G(x). G(x) is the generator polynomial of the code and is a monic polynomial of degree nxe2x88x92k: G(x)=xnxe2x88x92k+Gnxe2x88x92kxe2x88x921xnxe2x88x92kxe2x88x921+Gnxe2x88x92kxe2x88x922xnxe2x88x92kxe2x88x922+ . . . +G1x+G0, (P(x) has degree at most nxe2x88x92kxe2x88x921. I(x) is a polynomial of degree at most kxe2x88x921 with the k coefficients being the k information symbols, so C(x) is a polynomial of degree at most nxe2x88x921 with coefficients being the n codeword symbols.
Most popular architectures that implement polynomial division for systematic Reed-Solomon encoding comprise feedback shift registers that are composed of delay elements, GF element multipliers, and GF element adders as shown in FIG. 3. The delay elements D are initialized with zero symbol values. The information symbols are shifted into the register one at a time, highest order element first (Ikxe2x88x921). During each clock cycle of the register, the GF element held in the last delay element (leftmost) is fed back to nxe2x88x92k multipliers that compute the product of the feedback element with the feedback register multiplier elements G0 through Gnxe2x88x92kxe2x88x921. Because the finite field has a power of 2 number of elements, subtraction and addition are the same operation.
At each stage of the feedback register the products are added to the stored elements in the previous stage and the result is stored in the following stage. After clocking the register n times the elements stored in the delay elements D are the remainder of the division, or the parity elements that constitute the coefficients of the parity polynomial P(x). FIG. 4 shows a simplified feedback shift register that uses a pre-shifted I(x) to compute the remainder in only nxe2x88x92k clock cycles of the register.
It is important to understand that the architectures shown in FIGS. 3-4 evolved form a desire to efficiently implement Reed-Solomon encoders with circuit elements. In a typical encoder design, the three types of circuit elements (delays, GF adders, and GF multipliers) are individually optimized and then put together to perform the desired remainder computation operation. This type of encoder architecture can be emulated on a general purpose digital signal processing (DSP) platform. However, while either the GF multiply or the GF add can be implemented efficiently (depending upon the particular GF representation used), they cannot both be implemented efficiently simultaneously. For example, one particular representation allows GF adds to be computed with a simple exclusive-OR operation of the binary components of the two elements. In general, this can be implemented in one cycle of a DSP. However, for this same GF element representation, the GF multiply requires a large number of cycles to compute.
A GF multiplication table can be employed to reduce the number of cycles required to multiply two GF elements. However, a GF multiplication table can require a large amount of memory, and memory lookup to determine the product of two GF elements can also be somewhat time consuming.
The present invention provides a simplified finite field (Galois field or GF) multiplication table which is decimated and interleaved.
This has the advantages of allowing general purpose digital signal processors (DSPs) to efficiently perform Reed-Solomon encoding and thereby eliminating the need for specialized feedback shift register circuitry.